Generally speaking, a liquid crystal display device or an organic EL (Electro Luminescence) display device of an active matrix type includes: a substrate on which a thin film transistor (Thin Film Transistor; hereinafter also referred to as “TFT”) is formed as a switching element for each pixel (hereinafter also referred to as “TFT substrate”); a counter substrate on which a counter electrode, color filters, and the like are formed; and an optical modulation layer, e.g., a liquid crystal layer, provided between the TFT substrate and the counter substrate.
On the TFT substrate, a plurality of source lines, a plurality of gate lines, and a plurality of TFTs respectively disposed at intersections therebetween, pixel electrodes for applying a voltage across the optical modulation layer such as a liquid crystal layer, storage capacitor lines and storage capacitor electrodes, and the like are formed. Moreover, at an end portion of the TFT substrate, terminal portions for allowing the source lines and gate lines to be respectively connected to input terminals of a driving circuit are provided. The driving circuit may be formed on the TFT substrate, or on a separate substrate (circuit board).
The construction of a TFT substrate is disclosed in Patent Document 1, for example. Hereinafter, with reference to the drawings, the construction of a TFT substrate disclosed in Patent Document 1 will be described.
FIG. 15(a) is a schematic plan view showing the TFT substrate in outline, and the FIG. 15(b) is an enlarged plan view showing one pixel of the TFT substrate. FIG. 16 is a cross-sectional view of a TFT and terminal portions of the semiconductor device shown in FIG. 15.
As shown in FIG. 15(a), the TFT substrate includes a plurality of gate lines 2016 and a plurality of source lines 2017. Each region 2021 surrounded by these lines 2016 and 2017 defines a “pixel”. In a region 2040 of the TFT substrate other than the region (displaying region) where the pixels are formed, a plurality of connecting portions 2041 for allowing the plurality of gate lines 2016 and source lines 2017 to be respectively connected to a driving circuit are provided. Each connecting portion 2041 constitutes a terminal portion for providing connection to external wiring.
As shown in FIG. 15(b) and FIG. 16, a pixel electrode 2020 is provided so as to cover each region 2021 defining a pixel. Moreover, a TFT is formed in each region 2021. The TFT includes a gate electrode G, gate insulating films 2025 and 2026 covering the gate electrode G, a semiconductor layer 2019 disposed on the gate insulating film 2026, and a source electrode S and a drain electrode D respectively connected to both end portions of the semiconductor layer 2019. The TFT is covered by a protection film 2028. An interlayer insulating film 2029 is formed between the protection film 2028 and the pixel electrode 2020. The source electrode S of the TFT is connected to a source line 2017, whereas the gate electrode G is connected to a gate line 2016. The drain electrode D is connected to the pixel electrode 2020 within a contact hole 2030.
Moreover, a storage capacitor line 2018 is formed in parallel to the gate line 2016. The storage capacitor line 2018 is connected to a storage capacitor. Herein, the storage capacitor is composed of a storage capacitor electrode 2018b which is made of the same conductive film as the drain electrode, a storage capacitor electrode 2018a which is made of the same conductive film as the gate line, and the gate insulating film 2026 interposed therebetween.
On the connecting portion 2041 extending from each gate line 2016 or source line 2017, the gate insulating films 2025 and 2026 and the protection film 2028 are not formed, but a connection line 2044 is formed so as to be in contact with an upper face of the connecting portion 2041. As a result, electrical connection between the connecting portion 2041 and the connection line 2044 is ensured.
As shown in FIG. 16, in the liquid crystal display device, the TFT substrate is disposed so as to oppose a substrate 2014 on which a counter electrode and color filters are formed, with a liquid crystal layer 2015 interposed therebetween.
When fabricating such a TFT substrate, the regions 2021 to become pixels (also referred to as “pixel portions”) and the terminal portions are preferably formed through a common process, so as to reduce increase in the number of masks and the number of steps.
In order to fabricate the aforementioned TFT substrate, it is necessary to etch away the portions of the gate insulating films 2025 and 2026 and the protection film 2028 that are located in the terminal deployment region 2040, and the portions of the gate insulating film 2025 and the protection film 2028 that are located in the regions where the storage capacitors are to be formed. Patent Document 1 discloses forming an interlayer insulating film 2029 by using an organic insulating film, and by using this as a mask, etching the insulating films 2025 and 2026 and the protection film 2028.
Patent Document 2 describes the construction of a pixel portion of a TFT substrate having channel-protection type TFTs. However, the TFTs in Patent Document 2 are produced by using a silicon film.
FIG. 17 is a cross-sectional view showing a portion of the TFT substrate which is described in Patent Document 2. In each pixel of the TFT substrate, a thin film transistor 1141 and a storage capacitor 1142 are provided. On the thin film transistor 1141 are formed a gate line 1102, a gate insulating film 1104, a semiconductor layer 1113 having a channel-forming region, a channel protection film 1108, a source region 1118, a drain region 1117, a drain electrode 1121, and a source line 1122. The thin film transistor 1141 is covered by a protection film 1127, with a pixel electrode 1131 being provided on the protection film 1127. The pixel electrode 1131 is connected with the drain electrode 1121 within a contact hole which is formed in the protection film 1127. The storage capacitor 1142 is constituted by a capacitor line 1151 (which is made of the same conductive film as the gate line 1102) and the pixel electrode 1131 as the electrodes, and the gate insulating film 1104 and the protection film 1127 interposed between the electrodes as the dielectric.
On the other hand, Patent Document 3 proposes use of halftone masks in a production method of a TFT substrate having channel-protection type TFTs, this being in order to reduce the number of masks to be used. However, the method of Patent Document 3 requires a complicated production process, thus possibly lowering the mass producibility. Moreover, since only one layer of insulating film is formed between the gate electrode and the source/drain electrodes, there is a possibility of short-circuiting between these electrodes.